1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having copper wiring.
2. Background Art
Copper (Cu) has been employed as a wiring material in semiconductor devices. Copper is advantageous in that it is lower in resistance than aluminum (Al), with its permissible current in reliability being greater by two or more orders of magnitude than Al. Accordingly, the comparison between copper and aluminum leads to the fact that when using copper in order to obtain the same level of wiring resistance, the film thickness can be made smaller, with the possibility that the capacitance between wiring is reduced.
On the other hand, copper has the problem that it exhibits a high diffusion velocity in a silicon (Si) film or a silicon oxide (SiO2) film. In order to solve this problem, it has been usual to provide a multi-layered wiring structure (see, e.g., Japanese Patent Laid-open No. 10-261715).
Reference is now made to a copper wiring procedure in a multi-layered wiring structure. Initially, a first trench is formed in a first silicon oxide film. After the formation of a barrier metal film for preventing copper from being diffused toward the inner walls of the first trench, copper is buried in the first trench to form a first wiring layer. Next, after the formation of a silicon nitride (Si3N4) film on the first silicon oxide film so as to cover the first wiring layer therewith, a second silicon oxide film is formed on the silicon nitride film. Subsequently, the second silicon oxide film and the silicon nitride film are, respectively, etched to form a via hole and a second trench. Thereafter, the via hole and the second trench are, respectively, formed with a barrier metal on the inner surfaces thereof, and copper is buried in the via hole and the second trench, thereby forming a via plug and a second wiring layer. According to the steps set out hereinabove, the first wiring layer and the second wiring layer are electrically connected with each other through the via plug to form copper wiring having a multi-layered wiring structure.
In the above copper wiring procedure, when the via hole and the second trench are formed, the second silicon oxide film is etched to reach the surface of the silicon nitride film. Then, the silicon nitride film is etched with a mixed gas of tetrafluoromethane (CF4) and oxygen (O2), or a mixed gas of trifluoromethane (CHF3) and oxygen as an etching gas. In this way, copper for forming the first wiring layer is exposed to at the bottom of the via hole.
However, a fluorine-based deposit derived from the etching gas for the silicon nitride film is left on the copper surface immediately after the etching, with the attendant problem that the reaction between the fluorine and the copper enables a fluorine-containing polymer film to be formed on the copper surface. The formation of such a polymer film creates such a state that a native oxide film on the copper surface is undesirably broken. In this condition, if the semiconductor substrate is removed to outside of the etching chamber, the copper reacts with moisture in air thereby causing the copper to be corroded.